In a prior art, signal detector requires a plurality of rectifiers. Each rectifier converts a received alternative current (AC) signal to a direct current (DC) signal. Then, a collection unit collects and adds the DC signals to generate a detection signal to evaluate the intensity of the received signal. The foresaid structure of the receiver may be usable, but has shortcomings as described below.
When connecting a set of amplifiers in cascade, a cascade effect may occur, so the frequency bandwidth of the receiver is seriously constrained. For example, if the 3 dB frequency bandwidth of each amplifier is fs, when connecting N amplifiers in cascade, the 3 dB frequency bandwidth of the whole structure becomes ft, and the relation equation is ft=fsx(21/N−1)1/2. Hence, when the number of stages increases, the overall frequency bandwidth reduces. In order to broaden the frequency bandwidth of the whole structure, high bandwidth amplifiers may be selected to be the amplifiers at all stages. However, this will inevitably increase power consumption. To avoid using high bandwidth amplifiers at all stages, the bandwidth of an amplifier at a latter stage would require a larger bandwidth. This would make the multi-amplifier structure more inconsistent and increase the difficulty of design. Moreover, when each amplifier has a gain As, N amplifiers connected in cascade will have a total gain At, the equation is At=(As)N. Hence, the gain error would accumulate stage by stage, making the accuracy of the gain vulnerable to temperature or process variations. A solution is required to solve the problems mentioned above in the field.